Traditionally, C4 (Controlled Collapse Chip Connection) bumps have been used to bond a chip to a chip carrier (substrate). The C4 bumps (solder bumps) can be made from conventional lead tin solder or newer lead-free solder mixtures. During the fabrication process, the C4 bumps are connected to an under bump metallurgy (UBM), which is the critical interface between the metal pad of the IC and the solder bump (C4). The UBM consists of many layers including, for example, sputtered TiW and Cu and plated Ni. The UBM must be reliable and robust in order to withstand reflowing of the C4 bumps. For without such robustness, the UBM can fail, e.g., result in an unacceptable undercut in a metal layer that can affect the current carrying capabilities of the entire structure. Currently, UBM structures include current density peaks which impact device performance due to electromigration effects.
In lead-free C4 bumps, solder interconnects consist of tin/copper, tin/silver and SAC alloys as a replacement for leaded solder interconnents. However, lead-free C4 bumps have higher melting points and stiffness compared to eutectic leaded solders. This results in a transfer of stress through the C4 joint during the assembly process (e.g., during a cooling cycle after reflow). This transfer of stress results in cracks in chip metallurgy under C4 bumps, which are named “white bumps” due to their appearance in sonoscan type inspection processes. These white bumps, in turn, can affect the current carrying capabilities of the C4 joint by placing a higher than average current density at other locations of the C4 joint. In the best case scenario, this leads to device impairment and in the worst case scenario this leads to a device failure.
It is also known that the current density in interconnect structures increases due to scaling of the structures. This increased current density degrades EM (electromigration) related reliability, which becomes an increasing concern as the size of the integrated circuit (IC) decreases. For example, as the size of the C4 bump continues to shrink, the peak current density in the UBM will dictate the time to fail for the C4 bump. For example, existing C4 bumps are already reaching their current limit at, for example, approximately 100 mA (e.g., for ASIC), approximately 200 mA (e.g., for organic servers) and approximately 300 mA (e.g., for ceramic). But, new trends to reduce the current size, as well as eliminate the underlying Al layer of the structure, will have a direct impact on the future C4 bumps' maximum current capability.
In view of the above, the effect of electromigration is an important consideration to take into account in applications where high direct current densities are used, such as in microelectronics and related structures. In fact, as noted above, electromigration is known to decrease the reliability of integrated circuits (ICs) and hence lead to a malfunction of the circuit. In the worst case, for example, electromigration leads to the eventual loss of one or more connections and intermittent failure of the entire circuit. Thus, with increasing miniaturization the probability of failure due to electromigration increases in VSLI and USLI circuits because both the power density and the current density increase. Also, due to the increased electromigration it has not been practical to: (i) eliminate the aluminum layer in the structure or (ii) remove Ag from the C4 structure or laminate or both, which would otherwise reduce white bump issues.
Also, back-end-of-line (BEOL) interconnects, consisting of metal wires and inter-level vias, carry high direct current (DC) in advanced integrated circuit (IC) chip technology. In particular, as IC chip technology advances, the current density required in these metal wires/vias increases with the ever-decreasing dimensions in IC chip technology. Also, self-heating by high current devices raises the temperature of nearby interconnects under circuit operation and makes use of high current carrying BEOL interconnects extremely challenging. For example, a device that uses high current and self-heats (e.g., a resistor, a bipolar transistor, etc.) may heat up an interconnect wire that couples to the device. The high current leads to electro-migration (EM) degradation of the interconnect (via and/or line), causing shorts or opens.
As a result, the current-carrying capability (or the Idc limit specified in the design manuals) is significantly reduced to avoid electro-migration degradation in interconnects. As an example, a direct current limit in a copper interconnect may be reduced by a factor of more than three resulting from a temperature rise of about 15° C. from, for example, 85° C. to 100° C., and by almost a factor of 20 at a 125° C. interconnect temperature. As a result, high direct current at elevated temperatures is almost impossible with conventional interconnect structures.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.